The present invention relates to a multilevel interconnection forming method for forming a semiconductor device.
In general, a semiconductor device tends to have a circuit configuration arranged in a multilevel interconnection structure. In this multilevel interconnection structure, contact holes serve as connecting portions between a device of a lower layer and an aluminum interconnection wiring of an upper layer, and via holes serve as connecting portions between aluminum interconnection wirings of upper and lower layers. Therefore, techniques for filling contact holes and via holes are significant for obtaining electric connection between a wiring and a device or between wirings each other. Hence, these holes are filled by forming an aluminum film by sputtering, or these holes are filled by forming a tungsten film by CVD (Chemical Vapor Deposition). For example, following three methods are known as a method for filling a connecting hole between wirings.
Sputtering Method
With a substrate heated to a high temperature of 450.degree. C. or more, an aluminum film is formed on the substrate by sputtering, so that a hole is filled by the aluminum film. Otherwise, with a processing vessel set to 1 air pressure or more, an aluminum film is formed on a substrate by sputtering, so that a hole is filled by the aluminum film.
Selective Tungsten Film Forming Method
On the basis of a property that a tungsten film is selectively deposited on a surface of electrically conductive material, a tungsten film is deposited on conductive material at a bottom of the hole, thereby to fill a hole.
All Surface Film Forming Etch Back Method
Using, for example, a WF.sub.6 gas as a treatment gas, a strong reducing gas such as an SiH.sub.4 (mono-silane) gas is made react with the WF.sub.6 gas, causing a gas phase reaction, so that a tungsten film is formed on the entire surface of a substrate, thereby to fill a hole. After the hole is filled with the tungsten film, etching-back is carried out to remove unnecessary portions of the tungsten film which are formed on the other part than the hole.
Among the above three methods, the all surface film forming etch back method which is used most mainly will be explained in details below with reference to FIGS. 6A to 6E.
FIGS. 6A to 6E show a procedure in which a via hole electrically connecting interconnection wirings is filled by the all surface film forming etch back method. As shown in FIG. 6A, an insulating film 4 made of, for example, SiO.sub.2 is formed on a substrate 2 of a semiconductor wafer. On the insulating film 4, a first wiring layer 6 made of a patterned aluminum film is formed. An anti-reflection film 8 made of, for example, a TiN film for performing excellent resist exposure is formed on the first wiring layer 6. In the figure, the reference numeral 10 denotes an interlayer dielectric film made of, for example, SiO.sub.2, and this interlayer dielectric film 10 covers all the upper surface of the substrate 2. In this case, respective electric elements are entirely covered by the interlayer dielectric film 10.
A via hole 12 is formed such that the hole reaches a first wiring layer 6 situated below the hole, at a predetermined position of the interlayer dielectric film 10. In case where the via hole 12 is filled by a tungsten film, a contact resistance may be increased or contact between tungsten and aluminum (of the first wiring layer 6) may be deteriorated, by a suction effect caused between tungsten and aluminum (of the layer 6) if tungsten of the tungsten film has a direct contact with aluminum (of the first wiring layer 6). In order to avoid such a drawback, a barrier metal 14 made of, for example, a Ti film or a TiN film is formed on the entire surface including the inner surfaces of the via hole 12, as shown in FIG. 6B, before filling the via hole 12 with a tungsten film. Thereafter, as shown in FIG. 6C, a tungsten film 16 is formed over the entire surface of the barrier metal 14, for example, by CVD. The via hole 12 is thus filled by the tungsten film 16. In the next, as shown in FIG. 6D, unnecessary surface portions of the tungsten film 16 and the barrier metal 14 are removed by etch back, to expose an interlayer dielectric film 10, and a second patterned wiring layer 18 made of aluminum is formed on the interlayer dielectric film 10 thus exposed (see FIG. 6E). Therefore, the second wiring layer 18 is electrically connected with the first wiring layer 6 through tungsten filled in the via hole 12.
Meanwhile, according to the sputtering method mentioned before, sputtering processing is carried out at a high temperature of 450.degree. C. or more, and it is therefore impossible to use organic material having a low dielectric constant and a low heat resistance which is expected as an interlayer dielectric film of the next generation. Further, in the sputtering method, excellent filling of a hole is realized by improving the adhesion of the filling film toward the sidewall of the via hole, and therefore, a TiN film or a Ti film must be provided as an adhesion layer. Accordingly, the number of film forming steps must be increased, and the structure thereby obtained has a higher contact resistance in comparison with a structure in which an Al portion is directly connected with another Al portion.
Further, according to the selective tungsten film forming method, tungsten having a higher resistance than aluminum is used, and therefore, a signal delay is caused, so that the operation speed of the semiconductor device is lowered. Consequently, the device cannot respond especially to a micro-processor or the like which has been required to achieve high speed operation. On the other hand, in the selective tungsten film forming method, upper and lower wiring layers containing aluminum are connected with each other by tungsten, and therefore, electro-migration or corrosion occurs, thereby lowering the reliability of the wirings. Further, if selective loss occurs due to impurities sticking to the surface of conductive material during formation of a tungsten film, a leakage is incurred between wirings.
Even in the all surface film forming etch back method shown in FIGS. 6A to 6E, tungsten having a high resistance is used, and therefore, there appears the same problem as in the selective tungsten film forming method, resulting in a high contact resistance at an interface between films. Also, in the all surface film forming etch back method, a barrier metal 14 which reduces electro-migration to maintain adhesion must be formed, and accordingly, the number of film forming steps is increased, so that a structure thereby obtained has a high resistance ratio in comparison with a structure in which an Al portion is directly connected with another Al portion. In addition, since processing for forming a tungsten film by CVD is carried out at a high temperature of 450.degree. C., low dielectric constant organic material having a low heat resistance cannot be used to form an interlayer dielectric film. Further, since the step coverage of the barrier metal 14 which also works as the adhesion layer decreases as the aspect ratio increases because of down-sizing of connection holes. The short of step coverage suppresses the via filled by tungsten deposition. In the worst case, holes cannot be filled.
As described above, if a via hole is filled with tungsten or aluminum by sputtering, various problems occur. In contrast, if a via hole is filled with aluminum by CVD, above-mentioned problems do not occur. This is because aluminum is the material of low cost with has a low resistance and excellent conductivity and CVD achieves a more excellent step coverage than sputtering to prevent occurrence of voids. Therefore, it is desirable that holes are filled with aluminum by CVD. In this case, however, aluminum is deposited in holes, crystallized with a relatively large grain diameter. Therefore, if aluminum is filled at volume ratio (occupation ratio) of 100% with respect to a hole, to obtain good electric connection between upper and lower layers, aluminum is deposited to nearly overflow from the hole so that a convex portion is formed on the upper side of the hole. If processing is carried out for a wiring to be formed above the hole, with the convex portion remaining there, the focus depth exceeds its tolerance range due to the height of the convex portion, in a photolithography step of the processing. It is therefore impossible to carry out photolithography processing with high accuracy.